The present invention relates generally to decoupling capacitors on programmable logic devices (PLDs), and more specifically to such decoupling capacitors for generating high effective capacitance at high noise frequencies and with high area efficiency.
It should be noted that the term PLD as used herein is intended to cover the broad space of programmable logic. This includes devices formed in a silicon semiconducting substrate commonly known as CPLDs (Complex Programmable Logic Devices) such as MAX® 7000® from Altera Corporation of San Jose, Calif., FPGAs (Field Programmable Gate Arrays) such as Stratix® from Altera, or Structured ASICs (metal programmable logic) such as HardCopy® from Altera.
As PLDs become more integrated into high-speed systems, high performance with excellent signal integrity becomes more important. Previously known high-speed system designs have utilized on-chip decoupling capacitors implemented through the use of standard, direct transistor gate capacitance. This known approach is implemented by using the gate capacitance of a transistor with an arbitrary width (W) and length (L) combination. Nevertheless, this is also not sufficient, because the parasitic resistances of the gate and the device channel limit the capacitor's frequency response and, therefore, cannot create a large amount of capacitance at high frequencies. Unfortunately, such high frequencies are inherent in power supply noise, which is exactly the application these capacitors are targeted to dampen.
Accordingly, it would be desirable to provide improved decoupling capacitor designs for generating high effective capacitance at high noise frequencies and with high area efficiency.